A “side-channel attack” is one where fundamental flaws in the encryption implementation method are targeted, as opposed to flaws in the cryptographic algorithm itself.

By means of analogy, if your cryptographic method is to go to a locked room to have a private conversation, then a spy doesn’t have to pick the lock if they can still hear you through the door. The locked-room security method itself isn’t flawed, but implementing it without a soundproof door has much the same result.

In this case:

The threat resides in the chips’ data memory-dependent prefetcher, a hardware optimization that predicts the memory addresses of data that running code is likely to access in the near future. By loading the contents into the CPU cache before it’s actually needed, the DMP, as the feature is abbreviated, reduces latency between the main memory and the CPU, a common bottleneck in modern computing. DMPs are a relatively new phenomenon found only in M-series chips and Intel’s 13th-generation Raptor Lake microarchitecture, although older forms of prefetchers have been common for years.

Security experts have long known that classical prefetchers open a side channel that malicious processes can probe to obtain secret key material from cryptographic operations. This vulnerability is the result of the prefetchers making predictions based on previous access patterns, which can create changes in state that attackers can exploit to leak information.

So, the encryption the chips use is solid, but some of the hardware employed can still leak data.