pastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 28 days agoSome Mnemonicssh.itjust.worksimagemessage-square13fedilinkarrow-up18arrow-down10
arrow-up18arrow-down1imageSome Mnemonicssh.itjust.workspastermil@sh.itjust.works to Programmer Humor@lemmy.ml · 28 days agomessage-square13fedilink
minus-square9point6@lemmy.worldlinkfedilinkarrow-up3·28 days agoI still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle
I still don’t know why this architecture went for a Double XOR as the NOP, I guess they were just flexing that the reference chip design could do both in a single cycle